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WP3200 integrated a high performance 32-bitprocessor core. The processor contains 4KInstruction cache, 2K Data cache and MMU withTLB; its operation frequency is user selectable100/75MHz. The processor is support LittleEndian Mode and EJTAG debug function.Supports 16M/64M/128M bit SDRAM with 2/4-banksize availability, its operation frequency is the sameas processor.2 banks of Static Memory interfaces which cansupport Mask ROM, Page Mode ROM, EPROM,E2PROM, SRAM and NOR Flash (linear type)NAND Flash (block type) controller interfacesProvide a 256-Byte hard-wired boot code that canchoose booting from normal ROM, NAND Flash,UART or EJTAG debugger interfacePCMCIA-like interface to support glue-lessconnected to WLAN 802.11b deviceTwo Integrated 10/100 Ethernet MACs and one10M PHYThere are 5 bus masters on the WP3200 includingCPU, Ethernet 1, Ethernet 2, USB andMemory-to-Memory DMA3 24-bit up counter Timers and supports Intervaltimer mode and Watchdog timer modes (onlyTimer 3)2 sets of full duplex UARTs, one high speed up to921K bps and one low speed up to 115.2K bpsUSB Device Controller Interface compliance withUSB specification v1.1Provide 16 bi-directional general-purpose I/O pins(shared with other function pins)Two internal PLLs use external 8MHz crystal oroscillatorNon-stop 32.768kHz clock to generate 1 Hz clockto provide real time clock and calendar function160 pins QFP Package
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